This advanced micro-credential provides specialized knowledge and practical expertise in the verification and testing of complex integrated circuits (ICs) and system-on-chip (SoC) designs. Aligned with EQF Level 7, the programme focuses on advanced verification methodologies, including SystemVerilog, UVM, formal verification, constrained-random testing, and coverage-driven approaches, as well as Design-for-Testability (DFT) techniques and fault analysis.

The learner will be able to:

1. Critically analyze advanced digital and mixed-signal IC architectures and their verification requirements.
2. Explain formal verification methodologies, constrained-random verification, and coverage-driven verification strategies.
3. Evaluate SystemVerilog, UVM (Universal Verification Methodology), and assertion-based verification techniques.
4. Analyze Design-for-Testability (DFT) techniques, including scan chains, BIST (Built-In Self-Test), and boundary scan (JTAG).
5. Assess fault models, automatic test pattern generation (ATPG), and yield analysis in semiconductor manufacturing.
6. Critically evaluate verification planning, risk management, and validation strategies in complex SoC designs.
7. Examine reliability, safety, and compliance standards (e.g., ISO 26262 for functional safety where applicable).

Design and implement advanced verification environments using SystemVerilog and UVM. Develop constrained-random testbenches and apply functional coverage metrics. Apply formal verification tools to validate design properties and identify corner-case failures. Implement and evaluate DFT strategies in digital IC designs. Perform fault simulation and ATPG analysis to optimize test coverage and minimize production defects. Analyze verification results and produce professional technical documentation and reports. Use industry-standard EDA tools for simulation debugging and verification management.

The learner will be able to:

1. Lead and manage verification strategies for complex ASIC/SoC projects.
2. Integrate verification and test planning within the overall IC design lifecycle.
3. Critically assess and improve verification methodologies to enhance design reliability and time-to-market.
4. Take responsibility for strategic decisions in verification environments under conditions of uncertainty.
5. Collaborate in multidisciplinary semiconductor design teams and communicate advanced technical findings effectively.
6. Ensure compliance with quality, safety, and industry standards in IC verification and testing processes.

IC Verification Engineer

SoC Validation Engineer

DFT Engineer

Semiconductor Test Engineer

ASIC Design Verification Specialist

• Bachelor’s degree (EQF Level 6) in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field
• or
• Equivalent professional experience in semiconductor or digital design

Applicants should have:

• Strong knowledge of digital logic design and HDL (Verilog/VHDL)
• Familiarity with semiconductor device fundamentals
• Basic understanding of simulation tools

120 Hours

Hybrid (Online & Offline)

Projects

Micro-Credential

Name: Soheil Salha
Email: ssalha@najah.edu

5.00

www.najah.ai

Stackable within a Professional Path

Department Approved: Yes
Faculty Approved: Yes
Approval Date: 2026-02-24

Level 7